The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications
RituRajLamsal1✉Emailrituraj.lamsal@mbust.edu.np
MamtaBhattarai2
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Madan Bhandari University of Science and TechnologyNepal2
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South Asian UniversityDelhiRitu Raj Lamsal1, Mamta Bhattarai2
1Madan Bhandari University of Science and Technology, Nepal
2 South Asian University, Delhi
Corresponding Author: rituraj.lamsal@mbust.edu.np
Abstract
The relentless scaling of complementary metal-oxide-semiconductor (CMOS) technology, as dictated by Moore's Law, has driven the semiconductor industry through multiple transistor architecture revolutions. The planar bulk MOSFET, after decades of dominance, was succeeded by the three-dimensional FinFET at the 22/16 nm node to overcome severe short-channel effects (SCEs). However, as scaling continues to the 5 nm node and beyond, the limitations of the FinFET have become apparent. This literature review examines the journey from FinFETs to the next-generation architecture: the Gate-All-Around (GAA) Nanosheet Field-Effect Transistor (NSFET). It covers the motivations for this transition, the advantages and challenges of nanosheet technology, and the future roadmap towards forksheet and complementary FET (CFET) architectures. This paper presents a comparative analysis of power and delay characteristics between 5nm FinFET and 3nm Gate All Around (GAA) Nanosheet technologies using the educational EDA tool. A standard CMOS inverter is used as a test vehicle for this analysis. Simulation results demonstrate a significant improvement in the power-delay product (PDP) for the 3nm Nanosheet technology, improvement in propagation delay compared to the 5nm FinFET, primarily due to superior electrostatic control enabling lower supply voltage operation. The findings underscore the critical importance of the transition to GAA architectures for next-generation applications in Artificial Intelligence (AI), Machine Learning (ML), and the Internet of Things (IoT), where computational efficiency and ultra-low power consumption are paramount.
Keywords
CMOS
FinFET
Nanosheet FET
Gate All Around
Low-Power Design, AIoT Hardware
1. Introduction:
1.1 The Era of the FinFET
The insatiable demand for higher processing power and superior energy efficiency in modern electronics, driven by transformative technologies like Artificial Intelligence (AI) and the Internet of Things (IoT), relentlessly pushes the boundaries of semiconductor technology [1]. This demand creates a dual challenge: IoT edge devices require ultra-low-power processors to operate autonomously for years on miniature batteries, while AI training and inference demand immense computational throughput within strict thermal budgets, making power density a first-order design constraint [2]. Meeting these demands hinges on the continued scaling of transistor technology. For decades, this scaling was successfully achieved through the planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). However, as gate lengths approached the sub-30 nm regime, the industry encountered fundamental physical barriers. The inability to maintain electrostatic control over the channel led to severe short-channel effects (SCEs), characterized by exponential increases in leakage current and threshold voltage roll-off, rendering further planar scaling impractical [3].
This crisis precipitated a fundamental architectural shift. The seminal work by Hisamoto et al. introduced the concept of a three-dimensional transistor, the precursor to the modern FinFET, which demonstrated significantly improved SCE immunity [4]. The FinFET architecture addressed the limitations of the planar device by raising a narrow silicon "fin" from the substrate, allowing the gate to wrap around three sides of the channel. This provided vastly superior electrostatic control compared to its planar predecessor [5]. The industry's adoption of FinFETs, led by Intel at the 22 nm node, marked a critical inflection point, enabling continued performance and density scaling for nearly a decade [6]. FinFETs offered compelling advantages, including higher on-state current (ION) for a given footprint, lower leakage current (IOFF), and a reduced subthreshold swing (SS).
Nevertheless, as scaling approaches the 5 nm node and beyond, the limitations of the FinFET architecture have become pronounced. Challenges in further fin width scaling, increased variability, and ultimately insufficient gate control—stemming from the gate only contacting three sides of the channel—lead to rising leakage currents, once again threatening the path of Moore's Law [7].
In response, the Gate-All-Around (GAA) transistor, specifically the Nanosheet FET (NSFET), has emerged as the designated successor to the FinFET. This architecture represents the logical culmination of 3D design, where the gate material completely surrounds a stack of horizontal silicon channels (nanosheets) [8]. This configuration provides the ultimate electrostatic control, effectively suppressing SCEs at the 2 nm node and below. A key benefit of this enhanced control is the ability to further reduce the operating voltage (VDD), which quadratically reduces dynamic power consumption and directly lowers leakage current [9]. These characteristics make GAA Nanosheet technology uniquely suited to address the critical need for high-performance, ultra-low-power hardware required for the next generation of AI and IoT applications [1, 2].
1.2 Limitations of the FinFET at Scaled Nodes
Despite its success, the FinFET faces fundamental physical limitations as the contacted poly pitch (CPP) and fin pitch are scaled down below 5 nm. Key challenges identified in the literature include:
Electrostatic Control: In a FinFET, the gate only wraps around three sides of the channel, leaving a bottom interface that is vulnerable to leakage paths. At ultra-scaled fin widths, variability in fin patterning and line-edge roughness becomes a significant issue for performance and yield [10].
Drive Current Limitations: The drive current of a FinFET is proportional to the fin height. To increase current, designers must either increase fin height (leading to difficult high-aspect-ratio etching and filling processes) or place multiple fins in parallel (consuming more area and increasing parasitic capacitance) [11].
VT Tuning and Work Function Metal Deposition: Conformal deposition of work function metals (WFM) on the three-dimensional fin structure becomes increasingly challenging with pitch scaling. Inadequate WFM deposition leads to poor threshold voltage (VT) control and variability [12].
These limitations necessitated a new architecture with even more robust electrostatic integrity: the Gate-All-Around (GAA) transistor.
1.3. The Gate-All-Around Nanosheet FET: A Superior Successor
The Nanosheet FET represents the logical evolution beyond the FinFET. Instead of a vertical fin, the NSFET features multiple horizontal sheets of silicon stacked on top of one another, with the gate material wrapping around each sheet completely. This true GAA structure provides the ultimate electrostatic control, effectively suppressing SCEs at the sub-5 nm node [13].
Key Advantages of NSFETs:
Enhanced Electrostatic Control: The GAA configuration provides superior control over the channel, resulting in a near-ideal subthreshold swing and significantly reduced drain-induced barrier lowering (DIBL) compared to FinFET at the same gate length [14].
Higher Drive Current per Footprint: The drive current is proportional to the total width of the nanosheet. By stacking multiple sheets vertically, a much larger effective width can be achieved within the same footprint as a single fin, leading to higher performance without area penalty [15].
Better VT Tunability: The structure allows for independent tuning of nanosheet thickness and width, providing an additional knob for designers to optimize performance and power [16]. Furthermore, WFM deposition on horizontal surfaces is generally considered more manageable than on complex fin sidewalls.
1.4 State of the Art Global Foundries for Nanosheet Fabrication
Samsung Foundry currently stands as the primary manufacturer of chips utilizing nanosheet transistors, having achieved a significant industry milestone by initiating volume production of its 3nm node with Multi-Bridge-Channel FET (MBCFET™) technology in 2022. This accomplishment positioned Samsung as the pioneer in commercializing the Gate-All-Around (GAA) architecture [17]. The competitive landscape, however, is dynamic. Taiwan Semiconductor Manufacturing Company (TSMC), the global foundry leader, is preparing to introduce its own nanosheet technology with a planned volume production of its 2nm (N2) node in 2025 [18, 19]. Meanwhile, Intel Foundry's path has involved a strategic pivot. While the company developed its Intel 20A node—featuring its RibbonFET GAA technology—as a crucial testbed for foundational innovations, it announced a significant shift in September 2024 [20]. Intel canceled the 20A node for commercial production, opting instead to leverage external foundry partners like TSMC for products such as its Arrow Lake CPUs. This decision, aimed at cost-saving and resource optimization, allows Intel to redirect efforts toward accelerating the volume production of its more advanced 18A (1.8nm-class) node.
Consequently, while Samsung presently leads in production volume, the industry is converging on GAA technology. By 2025, both Samsung and TSMC are projected to have nanosheet-based processes in high-volume manufacturing. Intel aims to join them with its refined 18A node, collectively establishing GAA transistors as the new industry standard for the most advanced semiconductor nodes.
Foundry / Company | Technology Node | Name for Nanosheet Tech | Status (as of 2024) |
|---|---|---|---|
Samsung Foundry | 3nm (SF3), 2nm (SF2) | MBCFET™ | In Production (since 2022 for 3nm) |
TSMC | 2nm (N2) | Nanosheet (GAA) | Volume Production planned for 2025 |
Intel Foundry | 20A (2nm-class) | RibbonFET | Planned for 2024 ( Cancelled later) |
2. Materials and Methods
The analysis was conducted using Microwind version 3.9, an integrated circuit design and simulation tool for educational purposes. It features a built-in MOS scaling utility and a basic model for GAA transistors, allowing for a first-order comparison of different technology nodes [21]. Figure 1 illustrates the parameters associated with FinFET and nanosheet FET. It is important to note that the results are based on predictive and simplified models and are intended for trend analysis rather than absolute accuracy.
Fig. 1
(a) FinFET Parameters (b) Nanosheet FET Parameters
2.2 Test Vehicle
A standard CMOS inverter was chosen as the fundamental test vehicle for this analysis. The layout and three dimensional model is shown in Fig. 2 and Fig. 3 for FinFET and GAA Nanosheet respectively. Its simplicity allows for clear isolation and measurement of intrinsic device properties like delay and switching power.
Fig. 2
FinFET Inverter Layout, 3d view and layers
Fig. 3
GAA Nanosheet Inverter Layout, 3d view and Layers
2.3 Simulation Setup
Two separate designs were created for 5nm FinFET Inverter and 2nm Nanosheet FET inverter as shown in Figs. 2 and 3. A supply voltage (VDD) of 0.65V was applied, consistent with industry projections for this node [22, 23].
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Fig. 4
Clock frequency and its parameters
For a fair comparison, both inverters were designed to drive an identical load capacitor (CL = 5fF). The input was driven by a pulse voltage source with a rise/fall time of 0.05ns and a period of 0.1ns.
2.4 Analysis Methodology
Transient Analysis: Used to measure the propagation delay tp from the 50% point of the input signal to the 50% point of the output signal.
Power Analysis: Power Consumption feature was used to obtain the average dynamic power consumption during switching.
DC Analysis: Used to plot the Voltage Transfer Characteristic (VTC) and estimate the static (leakage) power by measuring the current at stable input states (Vin = 0V and VIN=VDD).
3. Results and Discussion
Various analysis plots for 5nm FinFET are shown in Fig. 5. The DC analysis Fig. 5 (a) reveals the switching Characteristics of the inverter. The voltage verses time plot is shown in Fig. 5(b) similarly voltage vs current and frequency verses time plots are depicted in Fig. 5 (c) and (d) respectively. The simulation is run for 2 nano second in interval of 100ps. The power consumption is 19.134 microwatts at 27 degree celcius. The average delay is estimated around 10 ps. The noise margin is estimated as
High-level noise margin (NMH)
NMH = VOH–VIH ≈ 0.65 V – 0.33 V = 0.32 V
Low-level noise margin (NML) :
NML = VIL–VOL ≈ 0.28 V – 0.0 V = 0.28 V
Fig. 5
Various characteristics of FinFET Inverter. (a) Voltage vs Voltage, (b) Voltage vs Time, (c) Voltage vs Current, (d) Frequency Vs time
Similarly Fig. 6 depicts various characteristics of GAA nanosheet. Nanosheet shows lower power consumption 18.03 µW vs 19.219 µW. This demonstrates the better electrostatic control of GAA architecture and Lower leakage currents contribute to reduced static power.
(a)
Input Voltage vs Output Voltage (b) Voltage Vs Time
Fig. 6
Various characteristics of GAA nanosheet Inverter. (c) Voltage vs current, (d) Frequency vs Time
The VTC of the 2nm NSFET inverter is steeper and more ideal than that of the 5nm FinFET, indicating a higher gain and better noise margins. This is a direct result of the enhanced electrostatic integrity of the GAA structure, which leads to a sharper transition from the off-state to the on-state. The simulation results show a faster switching response for the 2nm Nanosheet inverter. Transient analysis was performed to compare the switching speed. The key insights drawn from the overall analysis is summarized below:
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Speed Improvement (Delay): The transition from a three-sided gate (FinFET) to a four-sided, full-wrap gate (GAA Nanosheet) provides ultimate electrostatic control. This suppresses drain-induced barrier lowering (DIBL) and allows for more aggressive channel scaling, resulting in a higher on-state current (ION) and thus faster circuit switching
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Power Improvement (Power): The foundational benefit of the GAA structure is its ability to maintain performance at a significantly lower threshold voltage (Vth) and supply voltage (VDD) without succumbing to leakage. Since dynamic power has a quadratic dependence on VDD, even a modest reduction in voltage yields substantial power savings. The 2nm node leverages this to operate at 0.55V, drastically cutting active power.
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Efficiency Improvement (PDP): The PDP metric combines speed and power. The Nanosheet's architecture delivers a "win-win" scenario: it is both faster and consumes less power per operation. This synergistic improvement makes the 2nm GAA technology vastly more energy-efficient than the 5nm FinFET node, which is essential for extending battery life in mobile devices and reducing the enormous energy footprint of data centers.
3.4 Implications for Emerging Technologies (AI, ML, IoT)
The results have profound implications:
Internet of Things (IoT): Emerging technology Internet of Things (IoT) is widely used in many sectors. The ultra-low power consumption directly translates to extended battery life for edge devices, enabling more complex and always-on sensing and processing at the edge [24, 33].
Artificial Intelligence/Machine Learning: AI chips, particularly those performing inference, are power-bound. A reduction in PDP allows for either more operations per second (higher performance) within the same thermal envelope or the same performance at a drastically reduced power budget, enabling AI on mobile and embedded devices [2, 25]. The faster delay also improves the clock frequency potential of AI accelerators.
4. Challenges in Nanosheet Fabrication
The transition to NSFETs introduces significant fabrication complexities, which are a major focus of current research:
Inner Spacer Formation: A critical innovation in NSFETs is the inner spacer, which isolates the source/drain epitaxy from the gate to reduce parasitic capacitance. Precise deposition and etchback of dielectric materials like silicon nitride (SiN) in the narrow gaps between nanosheets are extremely challenging [26].
Channel Release: Forming the GAA structure requires selectively etching away the sacrificial silicon-germanium (SiGe) layers from between the silicon nanosheets without damaging the Si channels or collapsing the stack. This requires highly selective etch chemistries [27].
Nanosheet Width Scaling and Strain: As the width of the nanosheets is reduced to improve electrostatics, the benefits of uniaxial strain from the source/drain stressors diminish, potentially impacting carrier mobility [28].
Morphological Stability: The mechanical stability of long, thin, and released silicon nanosheets is a concern, requiring robust processes to prevent deformation or collapse during fabrication [29].
5. Future Outlook: Beyond Nanosheets
Research is already looking beyond the NSFET. The Forksheet FET introduces a dielectric wall between the n-type and p-type nanosheets to reduce the n-p spacing further, enabling continued pitch scaling and reduced variability [30]. Further ahead, the Complementary FET (CFET) takes 3D integration to its logical conclusion by stacking nFETs on top of pFETs, effectively doubling the transistor density without increasing the silicon footprint [31].
6. Conclusion
The proliferation of AI and IoT applications across critical sectors including agriculture, healthcare, and manufacturing [32–35] has intensified the demand for high-performance computing architectures that operate under stringent power constraints.
The transition from FinFETs to Nanosheet FETs represents a necessary architectural shift to maintain the pace of Moore's Law. While FinFETs solved the SCE problems of planar devices, their limitations at ultra-scaled nodes have made the superior electrostatic control of the GAA Nanosheet essential. Although NSFET fabrication presents significant challenges in areas like inner spacer formation and channel release, the industry has identified pathways to overcome these hurdles. Nanosheet technology is now in early production at the 3 nm/2 nm nodes, establishing itself as the workhorse for the next decade of advanced CMOS, while research continues into more advanced architectures like the Forksheet and CFET. This study utilized the Microwind 3.9 simulation environment to perform a comparative analysis of 5nm FinFET and 2nm GAA Nanosheet technologies. The results conclusively demonstrate the superior performance of the Nanosheet architecture, showcasing improvement in speed and reduction in power consumption.These improvements are fundamentally linked to the enhanced electrostatic control of the GAA structure, which permits aggressive scaling of the supply voltage without sacrificing performance. This transition is not merely an incremental improvement but a necessary architectural shift to sustain the progress of Moore's Law. The findings underscore why the semiconductor industry is adopting GAA Nanosheet technology at the 3nm/2nm nodes to power the next generation of ultra-low-power, high-performance computing applications, from ubiquitous IoT sensors to powerful AI accelerators. Future work would involve using more advanced simulation tools with industry-standard compact models (e.g., BSIM-CMG) for greater accuracy.
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Funding:
No funding received for this work
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Authors DeclarationAuthors declare no conflict of interest
Acknowledgement:
The authors would like to acknowledge Microwind Simulation tool for its use in simulation and layout generation.
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