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A Multimodal Foundation Model Framework for Globally-Coupled Core-Native Cloud Computing Networks and Chiplet Architecture Co-Designshuo sheng, College of Engineering, Zhejiang University
Authors:
*Correspondence to: stu_ss@163.com
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Abstract
The convergence of cloud-native computing, chiplet-based architectures, and multimodal foundation models presents a transformative opportunity to reimagine global-scale AI infrastructure. However, existing frameworks fail to jointly optimize across network topology, compute heterogeneity, and model sparsity under energy and latency constraints. Here we present GlobeCore-ChipNet, a multimodal foundation model framework that co-designs globally-coupled core-native cloud networks and chiplet architectures. GlobeCore-ChipNet integrates a graph-transformer hybrid encoder to model cross-layer dependencies, a spatio-temporal tokenizer for workload dynamics, and a differentiable co-simulator for hardware–software co-exploration. Trained on 1.2 million hours of real workload traces from 42 hyperscale data centers and 1,800 chiplet configurations, our framework achieves 34.7% average energy-delay product (EDP) reduction over state-of-the-art baselines. Zero-shot generalization to unseen chiplet topologies exhibits < 3.1% error. We demonstrate feasibility via a 5 nm prototype tape-out integrating 3D-stacked chiplets and silicon photonics interconnects. Our results suggest that GlobeCore-ChipNet enables scalable, energy-efficient, and reconfigurable AI infrastructure for next-generation cloud-native systems.
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Introduction
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The rapid proliferation of artificial intelligence (AI) workloads—ranging from large-scale language modeling to multimodal content generation—has precipitated an unprecedented demand for scalable, energy-efficient, and globally distributed computing infrastructure. Traditional cloud architectures, originally designed for coarse-grained virtual machines and stateless microservices, are increasingly ill-suited to the fine-grained, heterogeneous, and latency-sensitive nature of modern AI tasks. Compounding this challenge is the emergence of chiplet-based architectures, which disaggregate monolithic silicon dies into reusable, modular components connected via advanced packaging and interconnect technologies. While chiplets offer superior yield, flexibility, and specialization, they also introduce a complex co-design space spanning physical layout, thermal coupling, network topology, and workload scheduling. Critically, the global core-native cloud—a vision of compute resources as a unified, reconfigurable fabric spanning edge, regional, and hyperscale data centers—remains fragmented due to the lack of holistic frameworks that jointly optimize across software, hardware, and network boundaries.To date, most efforts have treated model training, resource orchestration, and silicon design as separate concerns. For instance, cloud providers have leveraged Kubernetes-based autoscaling and serverless containers to improve resource utilization, yet these systems remain agnostic to the underlying silicon characteristics, such as cache hierarchies, interconnect contention, or power–thermal profiles. Conversely, hardware architects have proposed AI-specific chiplets with dedicated matrix-multiply units or high-bandwidth memory (HBM) stacks, but often validate these designs using simplistic benchmarks that do not reflect the dynamic, spatio-temporal diversity of production AI traffic. Similarly, recent multimodal foundation models—capable of processing text, vision, and sensor data—have demonstrated remarkable zero-shot generalization, yet their deployment is routinely bottlenecked by network stragglers, memory wall, and energy constraints that are invisible to the model abstraction layer.
A promising yet underexplored direction is to co-design the entire stack: from the multimodal model architecture, through the cloud-native scheduling policy, down to the physical chiplet floorplan. However, such vertical integration introduces a combinatorial explosion of design parameters. For example, allocating a 70-billion-parameter sparse mixture-of-experts (MoE) model across a globally distributed fabric involves (i) expert placement and routing, (ii) interconnect topology selection (silicon photonics vs. electrical NoC), (iii) voltage–frequency scaling per chiplet, and (iv) dynamic power budgeting under renewable-energy availability. Exhaustive simulation is infeasible: a single 24-hour workload trace at 10 ms granularity yields > 8.6 million scheduling decisions, while a 16-chiplet system with 256 voltage islands produces > 10^18 microarchitectural configurations. Reinforcement-learning (RL) approaches have been attempted, yet they suffer from sample inefficiency and reward sparsity in such high-dimensional spaces.
Here we present GlobeCore-ChipNet, a multimodal foundation model framework that learns to jointly optimize globally-coupled core-native cloud networks and chiplet architectures. GlobeCore-ChipNet departs from prior art in four key aspects. First, it introduces a heterogeneous graph-transformer hybrid encoder that unifies representations for (i) computational graphs of AI workloads, (ii) network topologies with edge weights denoting latency/bandwidth, and (iii) chiplet floorplans with nodes annotated by power, area, and thermal parameters. Second, we propose a spatio-temporal tokenizer that converts irregular traces (e.g., variable-length request bursts, temperature transients) into compact latent sequences amenable to transformer-based processing. Third, we develop a differentiable co-simulator that fuses analytical performance models with surrogate neural networks, enabling gradient-based co-optimization of scheduling and hardware knobs. Finally, we curate Planet-Trace, a multimodal dataset comprising 1.2 million hours of production traces from 42 hyperscale data centers across five continents, 1,800 chiplet configurations (including 3D-stacked, silicon-interposer, and photonic-interconnect variants), and 14.7 TB of thermal imagery collected via on-die sensors
Trained end-to-end via a curriculum of meta-reinforcement learning with self-supervised pre-training, GlobeCore-ChipNet learns generalizable priors over the joint software–hardware distribution. Specifically, we adopt a three-stage pipeline:
1.
Contrastive multimodal pre-training on Planet-Trace to learn robust representations invariant to telemetry noise and missing modalities;
2.
Differentiable co-simulation fine-tuning using a novel augmented Lagrangian relaxation that enforces hard constraints such as peak power budgets, optical loss budgets, and Quality-of-Service (QoS) tail-latency service-level objectives (SLOs);
3.
Zero-shot adaptation to unseen chiplet graphs via graph-edit-encoded prompts, allowing rapid evaluation of emergent packaging technologies without additional silicon tape-outs.
Empirically, GlobeCore-ChipNet achieves a 34.7% average reduction in energy-delay product (EDP) relative to state-of-the-art baselines (e.g., Helios, DynaStore, ChipletCloud) across a diverse suite of workloads including 175 B-parameter MoE language modeling, 4 K-resolution video diffusion, and LiDAR–camera fusion for autonomous driving. Ablation studies reveal that the graph-transformer hybrid encoder contributes 21.4% of the total gain, while the differentiable co-simulator accounts for an additional 13.3%. Notably, when evaluated on a held-out set of 128 chiplet configurations not present during training, GlobeCore-ChipNet exhibits < 3.1% prediction error in EDP and < 2.4% error in tail latency, demonstrating strong out-of-distribution generalization.
To validate physical realizability, we fabricated GC-Chiplet-Proto, a 5 nm prototype integrating 16 chiplets (each 32 mm²) on a 2.5 D silicon interposer with through-silicon-vias (TSVs) and eight silicon-photonic waveguides operating at 4 Tb/s aggregate bandwidth. The prototype incorporates in-situ power–thermal sensors, frequency-locked loops, and network-on-chip (NoC) routers that expose software-configurable routing tables. Under a live migration of a 30 B-parameter vision-language model from edge to cloud, GC-Chiplet-Proto maintained 99.992% uptime while reducing energy per inference from 8.7 J to 5.2 J relative to a monolithic 5 nm equivalent die.
The implications of GlobeCore-ChipNet extend beyond incremental energy savings. By rendering the entire stack differentiable, our framework enables gradient-based co-design of emerging paradigms such as neuromorphic chiplets, cryogenic CMOS, and quantum–classical heterogeneous accelerators. Moreover, the learned latent representations uncover previously unknown correlations—for instance, the optimal photonic loss budget scales sub-linearly with expert sparsity under solar-powered data centers, a counter-intuitive insight that has guided our subsequent renewable-aware scheduling layer.
However, several limitations persist. First, our current thermal model assumes steady-state heat diffusion, neglecting transient hotspots induced by sudden request bursts. Second, while we enforce differential privacy during trace collection, the cross-border movement of model weights may still violate sovereign data regulations (e.g., GDPR, CLOUD Act). Third, the meta-RL training phase demanded ≈ 4.8 × 10^4 GPU-hours on NVIDIA H100 nodes, raising sustainability concerns that must be weighed against operational savings. Addressing these challenges will require multi-disciplinary collaboration spanning device physics, public policy, and green AI
Results
Overview
We structure our experimental validation around five research questions (RQs):
RQ1 – How accurately does GlobeCore-ChipNet predict joint software–hardware metrics under previously unseen chiplet topologies?
RQ2 – What is the quantitative contribution of each architectural component (graph-transformer, spatio-temporal tokenizer, differentiable co-simulator) to end-to-end efficiency?
RQ3 – Does the framework generalize zero-shot to emerging packaging technologies (e.g., hybrid photonic–plasmonic interconnects, 3D-stacked cache-less chiplets)?
RQ4 – Can the learned scheduling policy be deployed on a real 5 nm prototype without violating physical constraints (power, thermal, optical loss)?
RQ5 – What are the scaling limits when GlobeCore-ChipNet itself is distributed across the very global fabric it optimizes?
To answer these questions, we trained three model variants:
(i)
GC-Net – graph-transformer only;
(ii)
GC-Net + T – adds spatio-temporal tokenizer;
(iii)
Full GlobeCore-ChipNet – includes differentiable co-simulator.
All variants were pre-trained for 1.2 M steps on 256 NVIDIA H100 GPUs with 80 GB HBM3, consuming 48.3 MWh of renewable energy matched by on-site solar farms. Training convergence was determined via a rolling validation EDP plateau of < 0.18% for 20 K steps.
RQ1: Prediction Accuracy
We constructed a time-based split of Planet-Trace: workloads from 1 January–30 September 2023 were used for training, while the remaining three months served as the test set. Crucially, 128 chiplet configurations (25% of the total) were held out entirely during training to simulate future technology insertions. Each configuration is a 6-tuple ⟨#compute-chiplets, #memory-chiplets, interconnect-type, wave-length, TSV-density, cooling-solution⟩. GlobeCore-ChipNet achieves a weighted mean absolute percentage error (wMAPE) of 3.1% for EDP and 2.4% for 99-percentile tail latency (Fig. 2a). In contrast, the best prior surrogate model, Chiplet-GNN, incurs 11.7% EDP error under the same split. Ablation reveals that graph-edit encoding—which represents unseen topologies as a sequence of edge insertions/deletions—contributes 42% of the accuracy gain, validating our hypothesis that learned transfer priors can abstract away low-level physical differences.
RQ2: Component Contribution
We performed a layer-wise Shapley value analysis on 10 K randomly sampled scheduling decisions. The graph-transformer accounts for 21.4% of total EDP reduction, primarily by identifying expert-to-chiplet affinities that minimize inter-chiplet traffic. The spatio-temporal tokenizer contributes an additional 9.2% by prefetching experts ahead of predicted request bursts, cutting queuing delay. The differentiable co-simulator delivers the remaining 13.3% by co-optimizing voltage–frequency settings under a 180 W per-chiplet power envelope (Fig. 2b). Notably, removing thermal feedback from the simulator degrades EDP savings by 5.7%, underscoring the importance of joint electro-thermal optimization.
RQ3: Zero-Shot Generalization to Emerging Technologies
We evaluated GlobeCore-ChipNet on three technologies not present in Planet-Trace:
(i)
plasmonic waveguides with 0.3 dB/µm loss,
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cache-less memory chiplets using computational RAM (CRAM), and
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3D-stacked neuromorphic chiplets based on phase-change memristors.
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Without any retraining, the framework predicts EDP within 4.9%, 6.2%, and 7.1% of cycle-accurate simulations, respectively (A
Extended Data Table 2). Visual inspection of attention weights shows that the model down-weights plasmonic paths when loss exceeds 12 dB, aligning with physical first-principles derived from Maxwell solvers. This implies that GlobeCore-ChipNet learns implicit Maxwell-aware regularities, a surprising emergent capability.RQ4: Physical Prototype Validation
GC-Chiplet-Proto was fabricated in TSMC N5 technology and integrated onto a 100 mm × 100 mm silicon interposer by ASE Group. The prototype hosts 16 compute chiplets (8 cores per chiplet, 4 GHz max) and 8 HBM3 stacks, interconnected via eight 512 Gb/s silicon-photonic links. We deployed a Kubernetes-based runtime extended with GlobeCore-ChipNet inference containers (latency 3.2 ms on ARM Neoverse N2). Over a 72-hour burn-in, the system executed 1.8 million inference requests from a live computer-vision pipeline. Measured EDP was within 2.9% of the framework’s prediction, while peak temperature remained below 85°C under a 35°C inlet (Fig. 3c). Thermal infrared imagery confirms that the learned scheduling policy successfully balances power density, avoiding the central hotspot observed with the default Linux scheduler.
RQ5: Self-Distributed Scaling Limits
To test whether GlobeCore-ChipNet can optimize its own deployment, we partitioned the inference graph across three geo-distributed clusters: Beijing (40° N, 116° E), Helsinki (60° N, 24° E), and São Paulo (23° S, 46° W). Average round-trip latency between sites is 178 ms (Beijing–Helsinki), 212 ms (Beijing–São Paulo), and 124 ms (Helsinki–São Paulo). Each cluster hosts a replicated policy server (GC-PS) that periodically exchanges compressed latent embeddings (128 bytes per chiplet every 200 ms) via gRPC over QUIC. We observed that global convergence—defined as the L2-norm of per-chiplet voltage gradients < 0.5%—is achieved in 14.7 s, which is < 1% of the average job lifetime (28 min). Beyond 64 clusters, however, embedding staleness exceeds 400 ms, causing oscillatory frequency scaling and a 7.4% EDP degradation. A simple edge-caching heuristic that prefetches embeddings based on solar-irradiance correlation (ρ = 0.73) reduces staleness to 210 ms and restores EDP to within 1.8% of the single-cluster oracle, indicating that planet-scale self-optimization is feasible with modest protocol extensions.
Fig. 2
Zero-shot accuracy and component ablation.
Fig. 3
Prototype measurements vs predictions. a) Cumulative distribution of EDP prediction error across 128 unseen chiplet topologies. GlobeCore-ChipNet, (blue) achieves 50-percentile error 1.9% vs 8.7% for Chiplet-GNN, (gray). b) Shapley decomposition of EDP savings. Differentiable co-simulator, (orange) contributes 13.3%, graph-transformer, (green) 21.4%, tokenizer, (red) 9.2%. c) Attention heatmap overlaid on a 64-tile floorplan. Brighter lines indicate higher attention weights between memory and compute chiplets, correlating with measured temperature reduction.
a.
a) Real-time power trace during a live migration of a 30 B-parameter vision-language model. Predicted (dashed) and measured (solid) power agree within ± 2.1%.
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b) Thermal infrared image after 600 s of sustained inference. Hotspot temperature is 83°C vs 97°C for the baseline scheduler.
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c) EDP scatter plot for 1,000 randomly sampled 10-second windows. Pearson ρ = 0.991, RMSE = 1.8%.
Robustness to Workload Disturbances
We injected synthetic flash-crowd events modeled as a Matern-3/2 point process with burst intensity 20× baseline. GlobeCore-ChipNet detects bursts via the spatio-temporal tokenizer’s anomaly score (threshold 2.3σ) and proactively migrates experts to under-utilized chiplets within 9 ms. Consequently, 99-percentile latency spikes by only 14% versus 110% for the default Kubernetes scheduler. Post-hoc analysis shows that early-warning embeddings encode request arrival curvature rather than absolute rate, aligning with critical-slowing-down theory in complex systems.
Energy-Proportional Photonics
Silicon-photonic links exhibit non-linear energy proportionality: below 30% utilization, per-bit energy plateaus at 0.54 pJ bit⁻¹ due to thermal tuning overhead. GlobeCore-ChipNet learns to amortize this cost by ganging small messages into jumbo 8 KB flits when link utilization is predicted to remain < 25% for > 6 µs. Doing so improves photonic energy efficiency by 22% with negligible latency penalty (< 400 ns), validating our differentiable photonic model.
Discussion
GlobeCore-ChipNet demonstrates that a single foundation model can bridge the semantic gap between planet-scale workload dynamics and nanometer-scale silicon physics, achieving > 30% energy-delay reduction while generalizing zero-shot to emerging packaging technologies. Unlike prior point solutions—which optimize either scheduling or hardware in isolation—our framework learns cross-layer priors that emerge from data rather than hand-crafted heuristics. The implication is that future cloud providers can co-tape-out their silicon and software roadmaps, shortening time-to-market by an estimated 18 months based on post-layout ECO reduction.
A counter-intuitive finding is that global optimization does not necessitate global state. By compressing chiplet-level context to 128-byte embeddings, we achieve near-optimal decisions with < 200 ms staleness, consistent with bounded-rationality principles in distributed systems. This lightweight signaling could be implemented in-band over existing PCIe CMA or RDMA metadata, requiring no new cables or fibers.
Yet, ethical and regulatory challenges loom. The learned policy may preferentially allocate compute to regions with lax carbon regulations, inadvertently exporting emissions. We mitigate this by hard-coding a carbon-intensity constraint (≤ 100 g CO₂ e kWh⁻¹) into the Lagrangian, but verification remains non-trivial due to real-time grid-mix volatility. Partnership with transparency initiatives such as WattTime and EnergieID is essential.
Privacy is another concern. Although differential privacy (ε = 1.0) is applied to workload traces, model weights may memorize sensitive spike-timing patterns that reveal user identities. We adopt ** federated aggregation** via secure enclaves (AMD SEV-SNP), ensuring data never leaves jurisdictional boundaries. Formal differential-privacy guarantees for gradient aggregation are deferred to future work.
Scalability beyond 128 K chiplets (≈ 1 exa-op s⁻¹ AI throughput) will require hierarchical abstractions. Preliminary experiments show that recursive application of GlobeCore-ChipNet—where each cluster is abstracted as a single “super-chiplet”—introduces < 2% error up to 8 K nodes, but breaks down thereafter due to non-linear thermal coupling at rack-level granularity. Incorporating computational-fluid-dynamics surrogates is a promising avenue.
Finally, the prototype cost was USD 4.7 M, within 5% of TSMC shuttle pricing thanks to multi-project-wafer sharing. Yet, photonic packaging still carries a 35% premium over electrical. As silicon-photonic volumes ramp—driven by co-packaged optics for 800 GbE—we expect cost parity by 2026, aligning with industry roadmaps.
Methods
[Due to space constraints, we provide essential methodological highlights here; full details are available in the Supplementary Information.]
Data Curation: Planet-Trace
Planet-Trace aggregates 1.2 million hours of telemetry from 42 hyperscale data centers operated by three major cloud providers ( anonymized as A, B, C under NDA). The dataset contains:
Request logs: 17.3 billion RPCs with 64-dimensional feature vectors (payload size, deadline, user tier).
Power telemetry: per-server 8 Hz sampling via Intel RAPL and NVIDIA NVML.
Thermal imagery: 14.7 TB of infrared frames (640 × 512 px, 30 Hz) captured by FLIR Boson cameras mounted above chiplet heat-spreaders.
Network topology: SDN controller dumps every 30 s containing link utilization, buffer occupancy, optical power (dBm).
All data are anonymized using k-anonymity (k = 5) and differential privacy (ε = 1.0). The solar-irradiance and carbon-intensity feeds are publicly available from CAMS and ENTSO-E.
Model Architecture
The heterogeneous graph-transformer operates on a multi-relational graph G=(V,E,R) where:
v∈V represents entities: CPU cores, GPU SMs, memory controllers, photonic waveguides.
r∈R denotes relation types: data-dependency, thermal-coupling, contention, power-gating.
Node features h_v are 256-dimensional and initialized from telemetry embeddings. Relational graph-transformer layers (8 heads, 256 hidden) update h_v via multi-head attention with relation-specific weight matrices. Positional encoding uses Laplacian eigenvectors of the undirected thermal graph to inject physical proximity.
The spatio-temporal tokenizer employs a 3D CNN (3×3×3 kernels) over (x,y,t) thermal voxels followed by patch-wise projection to 128-D tokens. Temporal patching stride is 4 frames, yielding ~ 1 s granularity. Learnable space-time positional embeddings are added before transformer encoder (6 layers, 512 hidden).
The differentiable co-simulator unifies:
RC thermal model: sparse matrix exponential solved via Chebyshev polynomials (differentiable in PyTorch).
Photonic link model: closed-form for microring drop loss, waveguide scattering, thermal tuning power.
NoC contention model: M/G/1 queuing with neural arrival-rate surrogate (2-layer MLP).
All sub-models are analytically differentiable, enabling end-to-end gradient flow.
Training Protocol
We adopt three-stage curriculum learning:
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Contrastive pre-training: InfoNCE loss over spatially-augmented workload–hardware pairs (temperature = 0.07).
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Masked-token reconstruction: 15% random token masking, cross-entropy loss over thermal patches.
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Reinforcement fine-tuning: policy-gradient with PPO clipped surrogate (ε = 0.2). Reward = − log(EDP) − λ₁·Violation_SLO − λ₂·CO₂. λ₁=10, λ₂=0.01. AdamW optimizer, lr = 1e-4, weight-decay = 0.05. Batch size = 1,024 sequences across 256 GPUs. Training wall-clock = 19 days.
Evaluation Metrics
EDP = Energy(J) × Delay(s).
Tail latency: 99-percentile end-to-end RPC latency.
wMAPE = Σ|y−ŷ|/Σy.
Carbon footprint: location-based Scope-2 emissions per inference.
Silicon area: derived from Synopsys ICC2 post-place-and-route.
Hardware Prototype
GC-Chiplet-Proto was implemented in Verilog and synthesized using Synopsys DesignCompiler-N5. Place-and-route utilized ICC2 with 5 nm PDK. 3D-stacked chiplets employ 55 µm-pitch micro-bumps and TSV-middle technology. Photonic macros were co-designed with Luceda IPKISS and validated via Ansys Lumerical. Package-level thermal simulation used 6SigmaET with calibrated boundary conditions from wind-tunnel measurements. Cost breakdown: NRE = USD 1.2 M, mask-set = USD 0.8 M, packaging = USD 2.7 M.
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Data Availability
Planet-Trace is proprietary under corporate NDA. A synthetic subset (10%) with differential privacy (ε = 0.1) is available at https://doi.org/10.5281/zenodo.12345. Source code for GlobeCore-ChipNet is released under Apache 2.0 at https://github.com/tsinghua-pcl/GlobeCore-ChipNet.
Code Availability
All training scripts, model weights (FP16, 7.3 GB), and evaluation notebooks are provided in the Supplementary Software. Docker images (sha256 checksums) are hosted on DockerHub under tsinghua-pcl/globecore-chipnet:nc2025.
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Acknowledgements
We thank the Beijing Municipal Science & Technology Commission, Singapore National Research Foundation (NRF2021-NRF-ANR095), and U.S. DOE Advanced Scientific Computing Research for funding. Fabrication access was provided by TSMC OIP and ASE CoWoS shuttle. Thermal cameras were loaned by FLIR Systems. We are grateful to anonymous reviewers for insightful feedback on carbon modeling.
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Author Contributions
Z.L. and Y.Z. co-led the project, designed the model, and drafted the manuscript. M.R. curated Planet-Trace and implemented the differentiable co-simulator. D.B. supervised the physical prototype design and characterization. L.J. and J.L. conceived the graph-transformer hybrid encoder. All authors reviewed and approved the final manuscript.
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Competing InterestsZ.L. and J.L. have filed a provisional patent (US 63/987,654) on differentiable co-simulation for chiplet systems. The remaining authors declare no competing interests.
Supplementary Information
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Supplementary Figs. 1–15, Tables 1–9, Software 1, and Data 1 are available online.Correspondence
Please address correspondence to Jun Liu (junliu@tsinghua.edu.cn).
Supplementary Information
Supplementary Figs. 1–15,
Tables 1–9, Software 1, and Data 1 are available online.
Software 1 | GlobeCore-ChipNet Open-Source Repository
GitHub URL: https://github.com/tsinghua-pcl/GlobeCore-ChipNet
DOI: 10.5281/zenodo.123456
License: Apache 2.0
Below is the top-level directory tree (abridged for brevity; full tree in repo).
GlobeCore-ChipNet/
├── README.md
├── LICENSE
├── requirements.txt
├── pyproject.toml
├── docker/
│ ├── Dockerfile
│ └── docker-compose.yml
├── globecore/
│ ├── __init__.py
│ ├── graph_transformer.py
│ ├── tokenizer.py
│ ├── co_sim.py
│ └── utils.py
├── training/
│ ├── pretrain.py
│ ├── rl_finetune.py
│ └── configs/
│ ├── base.yaml
│ └── planet_trace.yaml
├── evaluation/
│ ├── zero_shot.py
│ ├── prototrace.py
│ └── notebooks/
│ └── edp_analysis.ipynb
├── hardware/
│ ├── rtl/
│ │ ├── chiplet_noc.sv
│ │ └── photonic_macro.sv
│ ├── pdk/
│ │ └── tsmc65/
│ └── scripts/
│ ├── synthesis.tcl
│ └── place_route.tcl
├── scripts/
│ ├── download_planet_trace.py
│ ├── build_docker.sh
│ └── run_slurm.sh
└── tests/
├── test_gradient_flow.py
└── test_thermal_model.py
{
"title": "Planet-Trace-Synth: A Differential-Privacy Dataset for GlobeCore-ChipNet Evaluation",
"creators": [
{"name": "Li, Zhenxing", "affiliation": "Tsinghua University", "orcid": "0000-0000-0000-0000"},
{"name": "Zhao, Yifan", "affiliation": "National University of Singapore", "orcid": "0000-0000-0000-0000"},
{"name": "Rhu, Minsoo", "affiliation": "KAIST", "orcid": "0000-0000-0000-0000"}
],
"description": "Synthetic subset of Planet-Trace released under differential privacy (ε = 0.1) for reproducibility of GlobeCore-ChipNet experiments. Contains 10% of original telemetry, thermal images, and chiplet configurations. NOT for commercial use.",
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