Method for 3D structure of measurement-free fault tolerant surface code

GunsikMin1Emailmgs3351@korea.ac.kr

JunHeo1✉Emailjunheo@korea.ac.kr

School of Electrical EngineeringKorea University02841SeoulRepublic of Korea

Abstract

Quantum error correction (QEC) is essential for mitigating decoherence in quantum computations, but many QEC schemes rely heavily on mid-circuit measurements, which introduce significant noise due to their high error rates in current hardware. To overcome this limitation, we propose a measurement-free QEC scheme based on the surface code, leveraging its topological robustness while eliminating the need for physical measurements during error correction. Our key innovation is a three-dimensional patch-based architecture that interlinks three logical qubit patches, enabling coherent error extraction and feedback without measurements. By transforming syndrome information into geometric correlations across patches, our design inherently suppresses measurement-induced errors while preserving the surface code’s fault-tolerant thresholds. We analyze the scheme’s performance under realistic noise models and demonstrate its advantages over traditional flag-based or Steane-type QEC in regimes where measurements dominate error rate. This work bridges the gap between measurement-free QEC and scalable surface code architectures, offering a path toward fault-tolerant quantum computing in systems where fast, high-fidelity measurements remain impractical.

Keywords

Measurement-Free Quantum Error Correction

Surface Code

Introduction

The implementation of robust quantum error correction (QEC) in noisy physical hardware stands as a fundamental requirement for achieving scalable, fault-tolerant quantum computationAharon97,Shor94,Shor96,Kitaev97. The threshold theorem guarantees that arbitrarily long quantum computations become possible if errors can be corrected faster than they accumulateKITAEV2003,Aliferis08. While fault-tolerant (FT) circuits inevitably introduce resource overhead in terms of qubits, gates, and time, they enable exponential suppression of logical errors provided physical error rates remain below a critical threshold. For a code correcting

$t$

errors, full fault-tolerance demands that no combination of

$t$

Pauli faults across any circuit components may cause logical failure.

Among various QEC approaches, the surface code has emerged as a leading candidate due to its high error threshold, nearest-neighbor interactions, and natural compatibility with 2D lattice-based architecturesSur12,XZZX,Stephens13. However, conventional surface code implementations face a fundamental bottleneck: their reliance on repeated mid-circuit measurements for stabilizer checks and real-time classical feedback process particularly vulnerable in current quantum hardwaresuppressing_2023, Graham23, Lis23.

All major quantum platforms—from superconducting transmons to trapped ions and neutral-atom arrays—struggle with measurement-induced limitations. Superconducting systems suffer from measurement crosstalk and error rates exceeding gate errors; trapped-ion and neutral-atom platforms face orders-of-magnitude slower measurement times compared to gate operations, exacerbated by demanding laser cooling requirementsBlinov02. While innovative solutions like sympathetic cooling and atom shuttling to dedicated readout zones have been proposed, the measurement bottleneck persists, motivating the search for alternative paradigms\cite{Saffman_2016}.

This challenge has spurred significant interest in measurement-free QEC schemes that maintain fault tolerance while eliminating physical qubit measurementsErcan18. Inspired by Steane-type error correction, such approaches employ logical ancilla qubits and coherent feedback to propagate syndrome informationPerlin23,Crow16. While promising demonstrations exist for Bacon-Shor and Calderbank-Shor-Steane (CSS) code, and non-FT surface code implementations, adapting these methods to topological codes without sacrificing scalability remains an open challengePaz10,Heuben23. Crucially, any practical solution must incorporate entropy removal mechanisms whether through qubit resets or fresh ancilla supplies while remaining compatible with native hardware operations.

Recent research has seen the emergence of quantum computing platforms designed to overcome the limitations of planar connectivity by incorporating three-dimensional (3D) architectures. Studies on quantum processors extending beyond planar connectivity to achieve 3D interconnection have been explored across various qubit platforms rosenberg_3d_2017,Mallek21,akhtar_high-fidelity_2023,bluvstein_logical_2024,bluvstein22. For instance, in superconducting systems, through-silicon vias (TSVs) have been utilized to enable non-planar connectivityrosenberg_3d_2017,Mallek21. Similarly, trapped-ion platforms have demonstrated inter-module connectivity across different microchipsAkhtar23, while atom arrays have achieved inter-zone connectivitybluvstein22. Furthermore, 3D quantum error correction codes leveraging such connectivity have been investigated Vasmer19,kubica_single-shot_2022]. Notably, a recent neutral atom array system achieved high-fidelity two-qubit gates, 3D connectivity, and fully programmable single-qubit rotations with mid-circuit readouts by implementing logical-level control within a zoned architecture \cite{bluvstein_logical_2024}. Additional studies\cite{mamgain_review_2023} emphasize the necessity of 3D qubit placement for efficient quantum computation, highlighting its significance in advancing quantum processor design. Another study Ha25 presents a 3D layout for logical qubits using surface codes and lattice surgery. This design works for systems that can ensure direct, three-dimensional connections between neighboring physical qubits.

In this work, we bridge this gap by introducing a 3D measurement-free surface code architecture that combines topological protection with efficient coherent syndrome processing. Our key innovations include :

Parallelized Syndrome Processing: A network of logical ancillas facilitates parallel error correction, reducing latency and circuit depth compared to sequential schemes

This paper is organized as follows. In Chapter 2, we introduce the basic measurement-free protocol that has been previously studied and the techniques developed to make it fault-tolerant. Chapter 3 proposes a measurement-free surface code protocol using swap operations in a 2D structure, and then introduces a 3D structured measurement-free surface code to complement it. Chapter 4 presents an analysis comparing the logical error rate performance of each protocol through numerical substitution of idling error and gate operation error values. Finally, the paper concludes with Chapter 5.

Previous Work

Fig. 1

Measurement free error correction protocol for bit flip code

Measurement-free quantum error correction paradigm replaces conventional destructive syndrome measurements with unitary feedback operations. For an

$[n,k,d]$

stabilizer code defined by generators

$\{S_1,...,S_{n-k}\}$

, the protocol executes error correction through ancilla-assisted syndrome extraction and coherent recovery operations. The syndrome extraction employs controlled unitary transformations:

$U_{ext}=\prod_{j=1}^{n-k}CNOT(S_j\rightarrow a_j)$

where

$CNOT(S_j\rightarrow a_j)$

represents a controlled operations applying stabilizer

$S_j$

to ancilla qubit

$a_j$

Correction is applied via multi-qubit controlled gates conditioned on ancilla states:

$U_{corr}=\sum_{S\in\{0,1\}^{n-k}}{P_S\otimes C_S}$

where

$P_S$

projects ancilla to syndrome state

$\ket{s}=\ket{s_1s_2s_3}$

, and

$C_S$

applies the appropriate Pauli correction. For the three-qubit bit-flip code example,

$\ket{0}_L=\ket{000}$

$\ket{1}_L=\ket{111}$

code with stabilizers :

$S_1=Z\otimes Z\otimes I \\ S_2=I\otimes Z\otimes Z \\ S_3=Z\otimes I\otimes Z$

With these syndromes we can detect error for valid syndromes satifying the parity check. The correction condition is implemented via :

$C_{3}NOT_{s_1s_2s_3\rightarrow q_i}=X_{q_{i}}$

$C_{3}NOT$

refers to an operation where three control qubits are assigned and the error correction protocol is triggered when the ancilla qubits

$(s_1,s_2,s_3)$

exhibit the syndrome patterns

$110, 101,$

and

$011$

, respectively. The scheme provides inherent protection against single extraction errors with detected through stabilizer redundancy (

$S_3=S_1S_2$

). The principles extend to surface codes by implementing

$X/Z$

stabilizers. The nine-qubit surface code has eight stabilizer generatorsand requires eight ancillas to correct arbitrary single-qubit errors. Four Z-type stabilizers

$S_1^{Z}=Z_{1}Z_{2}Z_{5}Z_{6};\ S_2^{Z}=Z_{4}Z_{5}Z_{8}Z_{9};\ S_3^{Z}=Z_{3}Z_{4};\ S_4^{Z}=Z_{6}Z_{7},$

and four X-type stabilizers

$S_1^{X}=X_{2}X_{3}X_{4}X_{5};\ S_2^{X}=X_{5}X_{6}X_{7}X_{8};\ S_3^{X}=X_{1}X_{2};\ S_4^{X}=X_{8}X_{9},$

and applying corrections through

$U_{corr,surf}=\sum_{S^X,S^Z}{P_{S^X,S^Z}\otimes C_{S^X,S^Z}}$

Fig. 2

All logical qubits within the same block must use the same quantum code, with the [7,1,3] Steane code serving as our primary example for circuit construction. The logical CNOT operation is implemented through transversal operations, where syndromes are first mapped to ancilla logical qubits before error correction is performed by resetting these ancilla qubits. Notably, separate circuits are required to handle Pauli X and Z errors due to their distinct propagation characteristics during CNOT operations - while X errors propagate forward (from control to target), Z errors propagate backward (from target to control), necessitating this differentiated approach for proper error correction.

The recent resultHeuben23 proposes a fault-tolerant quantum error correction (QEC) protocol that operates without measurements, relying entirely on coherent quantum operations. Their scheme uses three quantum registers: the first contains the logical data qubit encoded in

$n$

physical qubits (e.g., the [[7,1,3]] Steane code), the second is an equally sized logical auxiliary qubit initialized to

$\ket{+}_{L}$

$\ket{0}_{L}$

depending on whether X- or Z-errors are being corrected, and the third comprises unencoded ancilla qubits initialized to

$\ket{0}$

$\ket{+}$

To correct X-errors, a transversal CNOT gate is applied from the data block to the auxiliary block, coherently transferring error information without disturbing the logical state. This is followed by a syndrome extraction step where the auxiliary block is mapped to the ancilla register via a coherent operation, then reset. The syndrome is then copied back from the ancilla to the auxiliary block, and a quantum feedback operation applies a correction to the data register based on the extracted syndrome. A similar process is then applied to correct Z-errors, with appropriate Hadamard transformations on the auxiliary qubits.

The protocol is specifically designed to ensure fault tolerance at every stage. Transversal gates between blocks prevent error propagation within a single code block. Each correction is conditioned on a three-bit syndrome, implemented via multi-controlled gates (e.g.,

$C_3NOT$

$C_3Z$

), and resets between rounds eliminate the accumulation of correlated errors. The scheme guarantees fault tolerance against single faults, which only lead to correctable errors, resulting in a failure probability that scales as

$O(p^2)$

, significantly better than

$O(p)$

for non-fault-tolerant schemes.

This measurement-free approach is especially advantageous for error correcting code where fast, high-fidelity mid-circuit measurements are challenging—such as surface code. For platforms with physically limited connectivity, such as superconducting qubits, the surface code is still considered the most realistic and powerful quantum error correction scheme. This is due to its locality, which is optimized for 2D planar architectures, and its high error threshold, despite having a large overhead.. The authors present physical-level circuit implementations and hardware-specific adaptations of their scheme, highlighting its practical applicability and scalability.

Proposed Method

Measurement-free Surface Code

Fig. 3

An example of violated fault-tolerance of measurement free surface code for correcting Pauli-

$(X)$

error

In this chapter, we will describe a method for designing a fault-tolerant measurement-free surface code. When designing a circuit to detect and correct X-errors in a distance-3 surface code (as shown in Fig. 3), the implementation violates fault tolerance. The circuit employs a multi-CNOT gate for X-error correction following syndrome extraction. If an X-error occurs on the second syndrome qubit after extraction, the error propagates to the 1st, 5th, and 6th data qubits. This results in three errors on the data qubits,

$\ket{\psi}_L$

which exceeds the correction capability of a distance-3 error-correcting code (designed to correct only a single error), thereby breaking fault tolerance. To resolve this issue, we propose the modified circuit in Fig. 4.

Fig. 4

Fault tolerance by designing transversal CNOT gate in surface code circuit

AS shown in Fig. 4, we introduce an additional data qubit patch designated as a logical ancilla data qubit. In Fig.4, this appears Z stabilizer in surface code for using transversal CNOT to logical ancilla qubit.

$Z_{\psi_1}Z_{\psi_2}Z_{\psi_3}Z_{\psi_4}Z_{+1}Z_{+2}Z_{+3}Z_{+4}$

The surface code offers the significant advantage that stabilizer measurements require only local interactions between adjacent qubits on a 2D lattice. This avoids the need for long-range gates or complex qubit routing, thereby simplifying hardware implementation. However, to implement a measurement-free protocol, the system must be capable of performing error correction for both X-errors and Z-errors independently. To achieve this, we will employ two additional patches alongside the main data qubit patch, utilizing a total of three neighboring patches (one for syndrome extraction and error correction, plus two adjacent patches) to construct a single logical qubit.

Fig. 5

Circuit diagram for maintaining fault-tolerance. To prevent error propagation from SWAP operations, the protocol: (1) moves the target qubit to an adjacent position via SWAP, (2) performs the CNOT operation, and (3) executes inverse SWAP operations to return the qubit - ensuring fault-tolerance throughout the process.

Fig. 5 presents a Z stabilizer circuit for X-error correction, where the corresponding logical ancilla qubit

$\ket{+}_L$

may propagate errors through transversal CNOT gates when an

$X$

error occurs on the

$\ket{\psi}_L$

qubit. The circuit implements error correction by: (1) performing syndrome extraction on the affected syndrome qubits, (2) resetting the logical ancilla qubit, and (3) loading the stored syndrome values from the syndrome qubits to apply X-error corrections across all relevant syndromes. The reset operation is performed every time syndrome values are loaded from the syndrome qubits.

Fig. 6

This figure presents the sequence diagram for implementing transversal CNOT operations between corresponding data qubits in different blocks using these additional neighboring patches. To perform a CNOT operation between the middle-right data qubit,

$(a_6)$

in the primary data qubit patch and its counterpart in another block,

$(b_6)$

, qubit movement via SWAP operations becomes necessary. Since remote CNOT operations cannot be directly implemented in a 2D planar architecture, we first relocate the target qubit to an adjacent position through two SWAP operations, then perform the CNOT. This process is repeated through nine such steps to complete the full transversal CNOT operation across all data qubits in the patches. The protocol relocates the logical ancilla qubit adjacent to data qubits through two SWAP operations, then performs CNOT gates. This process is repeated across all 9 data qubits to implement a complete transversal CNOT operation.

On the other hand, a limitation of the superconducting system is that CNOT operations can only be performed between nearest-neighbor qubits. Since data qubits at the same position in different logical patches are not adjacent, they must be made adjacent to perform a physical CNOT operation, as shown in Fig. 6. This requires SWAP operations on the data qubits, and the operational method is illustrated in the diagram in Fig. 6. However, this approach presents a critical issue: when SWAP operations are performed within the same block, fault-tolerance may be compromised because errors can propagate through the SWAP operations, requiring additional safeguards. To address this, as shown in Fig. 5, we implement additional SWAP operations using qubits in the ancilla patch. Ultimately, by performing the sequence,

$SWAP_{b_{4}b_{5}} SWAP_{b_{5}b_{6}}(SWAP_{b_{4}b_{5}})^{\dagger}(SWAP_{b_{5}b_{6}})^{\dagger}=I$

We achieve an effect equivalent to the identity operation (I) where the qubits return to their original positions, while still obtaining the desired transversal CNOT operation during the intermediate steps.

3D Architecture Surface Code

In this chapter, we propose a measurement-free 3D surface code structure. Under the assumption that reset operations are feasible, we introduce a novel 3D topological code that eliminates the need for repetitive syndrome measurements.

Fig. 7

The X correction of the measurement-free fault-tolerant QEC implementation for the distance-3 surface code.

To achieve fault-tolerant quantum computation with a single logical qubit, we prepared two additional logical ancilla qubits. These ancilla qubits must be initialized in the states

$\ket{0}_{L}$

(for X stabilizer checks) and

$\ket{+}_{L}$

(for Z stabilizer checks), respectively. Due to the necessity of performing both X and Z stabilizer corrections, the error correction process requires three layers of operations to ensure reliable logical state preservation.

When stacking 2D layers, we construct three distinct logical state layers:

$(\ket{\psi}_{L})$

(for arbitrary logical states)

$(\ket{+}_{L})$

layer (for X-basis initializations)

The specific order of the three patches is not important. However, the logical ∣ψ⟩ patch must be in the center to enable a bidirectional transversal CNOT, so its position is the only constraint that needs to be considered. Transversal CNOT gates are applied between the corresponding logical qubits across these layers to enable fault-tolerant operations. For lattice surgery, only the

$\ket{\psi}_{L}$

layer undergoes merging and splitting processes to implement logical CNOT gates, while the other layers (

$\ket{0}_{L}$

and

$\ket{+}_{L}$

) remain passive. This selective manipulation minimizes physical resource overhead while preserving the reliability of the logical gate.

Fig. 8

The figure illustrates a structure performing transversal CNOT operations for a logical CNOT, showing how the patch logical

$(\ket{\psi}_L)$

state interacts with each patch to execute transversal CNOT in a 3D architecture.

We propose a 3D error correction code architecture with dimensions

$L\times L\times 3$

, specifically designed to enhance fault-tolerant quantum operations. This structure incorporates two additional layers dedicated solely to logical ancilla qubits for efficient syndrome extraction and error correction, while maintaining compatibility with conventional 2D lattice operations. The design enables transversal CNOT operations between logical qubits through strategic layer arrangement, eliminating the need for complex qubit routing in purely 2D configurations. This architectural method fundamentally addresses the limitations of 2D surface codes by providing native support for fault-tolerant logical operations.

Fig. 9

For a 3D layered patch logical qubit architecture, a

$(\ket{0}_L)$

state patch is designed to correct Pauli-Z errors, and a

$(\ket{+}_L)$

state patch is designed to correct Pauli-X errors.

The 3D configuration offers significant advantages over 2D approaches by removing the requirement for additional SWAP operations in transversal CNOT implementations. This optimization reduces circuit depth during error correction cycles, thereby substantially decreasing vulnerability to idling errors. Furthermore, the reduced gate operation count directly contributes to improved logical error rate performance. Our layered approach maintains all beneficial properties of surface codes while solving critical challenges in measurement-free error correction, particularly in minimizing both idle-time and gate-induced errors through its efficient 3D qubit connectivity.

Analysis of Methodology

Our comprehensive study evaluates the performance characteristics of both measurement-free and conventional measurement-dependent surface code architectures across three fundamental noise regimes. The quantum error model incorporates gate operations, state preparation, and measurement procedures through a depolarizing noise channel with parameter

$p$

. We specifically analyzed: decoherence-induced errors during measurement intervals, idling errors occurring between gate operations, and native imperfections in quantum gate implementations.

For temporal error components, we quantified decoherence effects by expressing idle qubit error probabilities as a function of the dimensionless ratio

$t/T$

₂, where

$t$

represents operation duration and

$T_{2}$

denotes the qubit coherence time. The investigation identifies distinct performance domains where each methodology excels. The measurement-free variant demonstrates enhanced robustness in regimes where measurement procedures constitute the dominant error source. Measurement time frames substantially surpass gate durations and ancilla qubit idling during measurement introduces prohibitive errors. For a qubit subject to purely Markovian dephasing dynamics, the idling error probability during time interval

$t$

can be expressed in terms of its coherence time

$T_2$

as:

$p_{idle}=\frac{1}{2}(1-\exp{(-\frac{t}{T_2})})$

Conversely, conventional measurement-based techniques maintain superior performance when high-speed, high-fidelity measurement implementation is feasible. Also, ancilla reset and measurement error rates remain below critical thresholds so, fast measurement cycles minimize temporal overhead. These findings establish a framework for selecting optimal error correction protocols based on device-specific parameters and operational constraints, providing crucial guidance for quantum hardware design and implementation strategies.

The measurement-free quantum error correction protocol is susceptible to two primary error sources: (1) idling errors during gate operations, and (2) intrinsic gate imperfections. In comparison, traditional measurement-based approaches are theoretically vulnerable to three error mechanisms, though practical implementations benefit from parallel stabilizer measurement capabilities. By performing simultaneous measurements across all data qubits, the measurement-based protocol reduces idling-related decoherence during syndrome extraction to negligible levels. Consequently, the dominant error sources in measurement-based systems typically become: (1) Gate operation errors

begin{table}[htb!]\begin{tabular}{|c|c|c|c|c|}\hlineResources & Distance &3D MFEC SC & 2D MFEC SC & Surface code \\ \hline\multirow{3}{*}{Qubits} & distance 3 &

$(35)$

$(17)$

\\ & distance 5 &

$(99)$

$(49)$

\\ & distance d &

$(4d^2-1)$

$(2d^2-1)$

\\ \hline\multirow{3}{*}{Circuit Depth} & distance 3 &

$(59)$

$(203)$

$(8)$

\\ & distance 5 &

$(158)$

& 558 &

$(8)$

\\ & distance d &

$(O(7d^2))$

$(O(23d^2))$

$(8)$

\\ \hline\end{tabular}\caption{Resource analysis of three protocols.}\end{table}The ratio of the logical error rate for the measurement-free protocol,

$p_{L}^{MF}$

, to that of the measurement-based protocol,

$p_{L}^{SM}$

, is expressed as follows:

$\frac{p^{MF}_{L}}{p^{SM}_{L}}=\frac{(cp)^{2}+(\tilde{c}p)^{2}+c\tilde{c}pp_{idle,op}} {(c'p)^{2}+(\tilde{c}'p_{idle,m})^{2}+c'\tilde{c}'pp_{idle,m}}$

For

$c$

and

$\tilde{c}$

, it is the number of gate operations and non gate opeation qubit depth in measurement free protocol, respectively

$p_{idle,op}$

represents the idling errror rate during operation. In proposed method,

$c'$

and

$\tilde{c}'$

appears the number of gate operations and the number of qubit in measurement based protocol, respectively and

$p_{idle,m}$

represents the idling errror rate during measurement.Consequently, the measurement-based protocol's logical error rate is dominantly determined by just two factors: (1) idling errors during measurement operations and (2) gate operation errors, with measurement errors constituting the most significant contributor among these.

In this manner, a generalization can be made for correctable errors

$t$

, and by calculating the number of logical operations, idling during operations, and measurement idling for a given distance

$d$

, the result can be expressed as

$\frac{p^{MF}_{L}}{p^{SM}_{L}}= \frac{(cp)^{t+1}+(cp)^{t}(\tilde{c}p_{idle,op})+...+(cp)(\tilde{c}p_{idle,op})^{t}+(\tilde{c}p_{idle,op})^{t+1}} {(c'p)^{t+1}+(c'p)^{t}(\tilde{c}'p_{idle,m})+...+(c'p)(\tilde{c}'p_{idle,m})^{t}+(\tilde{c}'p_{idle,m})^{t+1}}$

Fig. 10

Utility diagram comparing the performance of 3D structured protocols with surface code, and 2D structured protocols with surface code. In diagram (a), the red circle highlights where the 3D MFEC SC shows an advantage in logical error rate compared to the surface code. In diagram (b), the green diamond shape indicates where the 2D MFEC SC demonstrates an advantage in logical error rate over the surface code, but the required hardware measurement error rate for this advantage appears to be significantly different compared to the 3D version.

Figure 10 left graph compares the performance of the 3D structured MFEC SC and the measurement-based surface code protocol. The computing environment assumes a fixed idling error rate during operation,

$p_{idle,op}$

, at

$10^{-4}$

. In this scenario, the x-axis represents the computing environment with a physical error rate

$p$

for gate operations ranging from

$10^{-4}$

$10^{-3}$

. The y-axis compares the performance of the two protocols by varying the ratio of idling error during measurement to idling error during operation from 100 to 400. At a physical error rate

$p$

$10^{-4}$

, the results show that the proposed protocol can achieve performance gain when the measurement error and time, as indicated by the y-axis ratio, is approximately 210 times higher and longer(depicted in red circle) than the operation error and time.

As the physical error rate increases, the number of gate operations in the proposed protocol also increases. Therefore, to achieve a performance gain, the measurement error must be proportionally higher.

Figure 10 right graph compares the performance of the 2D MFEC SC protocol and the surface code. The numerical values of the parameters for performance comparison were kept the same as in the 3D structure. However, this protocol, which requires higher circuit depth and additional gate operations, can only show an advantage when the measurement error is significantly higher than in the 3D structure. For the 2D structure, at a physical error rate of

$10^{-4}$

, the protocol can achieve performance gain only when the measurement error rate is more than 800 times higher than the idling error during operation(depicted in green diamond shape).

Fig. 11

Performance comparison diagram of the three protocols. The red circle indicates where the 3D MFEC SC shows strength in logical error rate compared to the surface code. In the green diamond shape, both the 2D MFEC SC and 3D MFEC SC appear to demonstrate strength over the surface code in terms of the measurement error rate.

Fig.11 finally compares all three protocols. As assumed in the previous discussion, when the physical error rate is

$10^{-4}$

and the ratio of the measurement error rate to the idling error rate during operation is around 210, the proposed 3D structured protocol shows a performance gain. When this ratio is 800 or more, both protocols can achieve performance benefits, indicating their usability. This demonstrates that the proposed protocol can compensate when the measurement error rate is relatively critical.

Conclusion

In this work, we have presented a comprehensive framework for implementing measurement-free quantum error correction in a 3D lattice surface code architecture. Our approach fundamentally addresses the challenge of performing fault-tolerant operations without relying on syndrome measurements while preserving the surface code's inherent advantages of local stabilizer interactions and planar connectivity.

The proposed architecture shows particular promise for near-term quantum devices where measurement operations remain a significant bottleneck. By combining the surface code's natural robustness with measurement-free protocols, we have developed a practical pathway toward scalable fault-tolerant quantum computation. To enable fault-tolerant measurement-free error correction, our protocol requires the execution of transversal CNOT operations.

Key findings reveal that when implementing measurement-free error correction protocols in 2D lattice surface codes, the substantial overhead from SWAP operations demands measurement times exceeding gate operation times by a factor of 700 to achieve reasonable efficiency. Remarkably, our proposed 3D architecture reduces this requirement to just 180 times, demonstrating significant performance improvements.

Several critical requirements emerge from this study:\\

Future work should explore lattice surgery-based surface code protocols in 3D architectures.

Development of conditions for performing logical CNOT operations will be crucial for advancing this approach.

This research establishes important groundwork for overcoming one of surface code's most significant implementation challenges while maintaining its topological advantages. The principles developed here may extend to other quantum error correction paradigms, potentially enabling new architectures for fault-tolerant quantum computation.

GSM conceived the proposed method, GSM performed the simulations, derived the analytical equations, and prepared the figures. Both GSM, and JH contributed to the development of the core ideas, with JH supervising the project.

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

The authors declare that they have no conflict of interest.

Not applicable

Ethical review and approval were not required for this study.

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Fowler, Austin G. and Mariantoni, Matteo and Martinis, John M. and Cleland, Andrew N. (2012) Surface codes: Towards practical large-scale quantum computation. Phys. Rev. A 86: 032324 https://doi.org/10.1103/PhysRevA.86.032324, https://link.aps.org/doi/10.1103/PhysRevA.86.032324, American Physical Society, Sep, 48, 3

Bonilla Ataides, J. Pablo and Tuckett, David K. and Bartlett, Stephen D. and Flammia, Steven T. and Brown, Benjamin J. (2021) The {XZZX} surface code. Nature Communications 12(1): 2172 https://doi.org/10.1038/s41467-021-22274-1, April, Performing large calculations with a quantum computer will likely require a fault-tolerant architecture based on quantum error-correcting codes. The challenge is to design practical quantum error-correcting codes that perform well against realistic noise using modest resources. Here we show that a variant of the surface code —the XZZX code —offers remarkable performance for fault-tolerant quantum computation. The error threshold of this code matches what can be achieved with random codes (hashing) for every single-qubit Pauli noise channel; it is the first explicit code shown to have this universal property. We present numerical evidence that the threshold even exceeds this hashing bound for an experimentally relevant range of noise parameters. Focusing on the common situation where qubit dephasing is the dominant noise, we show that this code has a practical, high-performance decoder and surpasses all previously known thresholds in the realistic setting where syndrome measurements are unreliable. We go on to demonstrate the favourable sub-threshold resource scaling that can be obtained by specialising a code to exploit structure in the noise. We show that it is possible to maintain all of these advantages when we perform fault-tolerant quantum computation., https://doi.org/10.1038/s41467-021-22274-1, 2041-1723

{Google Quantum AI} (2023) Suppressing quantum errors by scaling a surface code logical qubit. Nature 614(7949): 676--681 https://doi.org/10.1038/s41586-022-05434-1, feb, Practical quantum computing will require error rates well below those achievable with physical qubits. Quantum error correction1,2 offers a path to algorithmically relevant error rates by encoding logical qubits within many physical qubits, for which increasing the number of physical qubits enhances protection against physical errors. However, introducing more qubits also increases the number of error sources, so the density of errors must be sufficiently low for logical performance to improve with increasing code size. Here we report the measurement of logical qubit performance scaling across several code sizes, and demonstrate that our system of superconducting qubits has sufficient performance to overcome the additional errors from increasing qubit number. We find that our distance-5 surface code logical qubit modestly outperforms an ensemble of distance-3 logical qubits on average, in terms of both logical error probability over 25 cycles and logical error per cycle ((2.914 ± 0.016)% compared to (3.028 ± 0.023)%). To investigate damaging, low-probability error sources, we run a distance-25 repetition code and observe a 1.7 × 10 −6 logical error per cycle floor set by a single high-energy event (1.6 × 10 −7 excluding this event). We accurately model our experiment, extracting error budgets that highlight the biggest challenges for future systems. These results mark an experimental demonstration in which quantum error correction begins to improve performance with increasing qubit number, illuminating the path to reaching the logical error rates required for computation., https://doi.org/10.1038/s41586-022-05434-1, 1476-4687

Blinov, B. B. and Deslauriers, L. and Lee, P. and Madsen, M. J. and Miller, R. and Monroe, C. (2002) Sympathetic cooling of trapped

$({\mathrm{Cd}}^{+})$

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Saffman, M (2016) Quantum computing with atomic qubits and Rydberg interactions: progress and challenges. Journal of Physics B: Atomic, Molecular and Optical Physics 49(20): 202001 https://doi.org/10.1088/0953-4075/49/20/202001, We present a review of quantum computation with neutral atom qubits. After an overview of architectural options and approaches to preparing large qubit arrays we examine Rydberg mediated gate protocols and fidelity for two- and multi-qubit interactions. Quantum simulation and Rydberg dressing are alternatives to circuit based quantum computing for exploring many body quantum dynamics. We review the properties of the dressing interaction and provide a quantitative figure of merit for the complexity of the coherent dynamics that can be accessed with dressing. We conclude with a summary of the current status and an outlook for future progress., IOP Publishing, oct, https://dx.doi.org/10.1088/0953-4075/49/20/202001

Graham, T. M. and Phuttitarn, L. and Chinnarasu, R. and Song, Y. and Poole, C. and Jooya, K. and Scott, J. and Scott, A. and Eichler, P. and Saffman, M. (2023) Midcircuit Measurements on a Single-Species Neutral Alkali Atom Quantum Processor. Phys. Rev. X 13: 041051 https://doi.org/10.1103/PhysRevX.13.041051, https://link.aps.org/doi/10.1103/PhysRevX.13.041051, American Physical Society, Dec, 22, 4

Lis, Joanna W. and Senoo, Aruku and McGrew, William F. and R\"onchen, Felix and Jenkins, Alec and Kaufman, Adam M. (2023) Midcircuit Operations Using the omg Architecture in Neutral Atom Arrays. Phys. Rev. X 13: 041035 https://doi.org/10.1103/PhysRevX.13.041035, https://link.aps.org/doi/10.1103/PhysRevX.13.041035, American Physical Society, Nov, 22, 4

Ercan, H. Ekmel and Ghosh, Joydip and Crow, Daniel and Premakumar, Vickram N. and Joynt, Robert and Friesen, Mark and Coppersmith, S. N. (2018) Measurement-free implementations of small-scale surface codes for quantum-dot qubits. Phys. Rev. A 97: 012318 https://doi.org/10.1103/PhysRevA.97.012318, https://link.aps.org/doi/10.1103/PhysRevA.97.012318, American Physical Society, Jan, 9, 1

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Perlin, Michael A. and Premakumar, Vickram N. and Wang, Jiakai and Saffman, Mark and Joynt, Robert (2023) Fault-tolerant measurement-free quantum error correction with multiqubit gates. Phys. Rev. A 108: 062426 https://doi.org/10.1103/PhysRevA.108.062426, https://link.aps.org/doi/10.1103/PhysRevA.108.062426, American Physical Society, Dec, 14, 6

Heu\ss{}en, Sascha and Locher, David F. and M\"uller, Markus (2024) Measurement-Free Fault-Tolerant Quantum Error Correction in Near-Term Devices. PRX Quantum 5: 010333 https://doi.org/10.1103/PRXQuantum.5.010333, https://link.aps.org/doi/10.1103/PRXQuantum.5.010333, American Physical Society, Feb, 25, 1

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Akhtar, M and Bonus, F and Lebrun-Gallagher, FR and Johnson, NI and Siegele-Brown, M and Hong, S and Hile, SJ and Kulmiya, SA and Weidt, S and Hensinger, WK (2023) A high-fidelity quantum matter-link between ion-trap microchip modules. Nat Commun 14: 531 https://doi.org/10.1038/s41467-022-35285-3

Bluvstein, Dolev and Levine, Harry and Semeghini, Giulia and Wang, Tout T. and Ebadi, Sepehr and Kalinowski, Marcin and Keesling, Alexander and Maskara, Nishad and Pichler, Hannes and Greiner, Markus and Vuleti ć, Vladan and Lukin, Mikhail D. (2022) A quantum processor based on coherent transport of entangled atom arrays. Nature 604(7906): 451--456 https://doi.org/10.1038/s41586-022-04592-6, https://doi.org/10.1038/s41586-022-04592-6, 1476-4687

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Akhtar, M. and Bonus, F. and Lebrun-Gallagher, F. R. and Johnson, N. I. and Siegele-Brown, M. and Hong, S. and Hile, S. J. and Kulmiya, S. A. and Weidt, S. and Hensinger, W. K. (2023) A high-fidelity quantum matter-link between ion-trap microchip modules. Nature Communications 14(1): 531 https://doi.org/10.1038/s41467-022-35285-3, https://doi.org/10.1038/s41467-022-35285-3, 2041-1723

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Bluvstein, Dolev and Evered, Simon J. and Geim, Alexandra A. and Li, Sophie H. and Zhou, Hengyun and Manovitz, Tom and Ebadi, Sepehr and Cain, Madelyn and Kalinowski, Marcin and Hangleiter, Dominik and Bonilla Ataides, J. Pablo and Maskara, Nishad and Cong, Iris and Gao, Xun and Sales Rodriguez, Pedro and Karolyshyn, Thomas and Semeghini, Giulia and Gullans, Michael J. and Greiner, Markus and Vuleti ć, Vladan and Lukin, Mikhail D. (2024) Logical quantum processor based on reconfigurable atom arrays. Nature 626(7997): 58--65 https://doi.org/10.1038/s41586-023-06927-3, https://doi.org/10.1038/s41586-023-06927-3, 1476-4687

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