﻿SAIF power run started: 2026-11-02T22:22:07
Part: xa7z010clg225-1I | Implementation clock: 5.5 ns | SAIF window: 20000 words | TREADY duty: 100 % | zero key: False | warm-up: 5
Vivado : C:\Xilinx\Vivado\2019.1\bin\vivado.bat

=== [1/4] V0_xoshiro_only ===
  AXI4-Lite address width: 7 bits; N_WORDS at 7'h10, AP_CTRL at 7'h00
  [1/4] Vivado OOC implementation + timing netlist ...
  implemented: LUT=685 FF=847 (compare with the ablation table: 685/853/794/934 LUT)
  [2/4] compile + elaborate (timing simulation, SDF back-annotation) ...
  [3/4] simulate 113330 ns and capture SAIF (this is the slow step) ...
  words transferred in simulation: 20000 (expected 20000)
  [4/4] Vivado report_power with SAIF ...
  LUT=685 FF=847 | Pdyn=0.027 W Pstatic=0.090 W Ptotal=0.117 W | confidence=High | nets matched: 71%   (1373/1929)

=== [2/4] V1_plus_weyl ===
  AXI4-Lite address width: 7 bits; N_WORDS at 7'h10, AP_CTRL at 7'h00
  [1/4] Vivado OOC implementation + timing netlist ...
  implemented: LUT=853 FF=975 (compare with the ablation table: 685/853/794/934 LUT)
  [2/4] compile + elaborate (timing simulation, SDF back-annotation) ...
  [3/4] simulate 113330 ns and capture SAIF (this is the slow step) ...
  words transferred in simulation: 20000 (expected 20000)
  [4/4] Vivado report_power with SAIF ...
  LUT=853 FF=975 | Pdyn=0.040 W Pstatic=0.090 W Ptotal=0.130 W | confidence=High | nets matched: 75%   (1775/2357)

=== [3/4] V2_plus_tent ===
  AXI4-Lite address width: 7 bits; N_WORDS at 7'h10, AP_CTRL at 7'h00
  [1/4] Vivado OOC implementation + timing netlist ...
  implemented: LUT=794 FF=943 (compare with the ablation table: 685/853/794/934 LUT)
  [2/4] compile + elaborate (timing simulation, SDF back-annotation) ...
  [3/4] simulate 113330 ns and capture SAIF (this is the slow step) ...
  words transferred in simulation: 20000 (expected 20000)
  [4/4] Vivado report_power with SAIF ...
  LUT=794 FF=943 | Pdyn=0.037 W Pstatic=0.090 W Ptotal=0.127 W | confidence=High | nets matched: 67%   (1426/2136)

=== [4/4] V3_full_original ===
  AXI4-Lite address width: 7 bits; N_WORDS at 7'h10, AP_CTRL at 7'h00
  [1/4] Vivado OOC implementation + timing netlist ...
  implemented: LUT=934 FF=1071 (compare with the ablation table: 685/853/794/934 LUT)
  [2/4] compile + elaborate (timing simulation, SDF back-annotation) ...
  [3/4] simulate 113330 ns and capture SAIF (this is the slow step) ...
  words transferred in simulation: 20000 (expected 20000)
  [4/4] Vivado report_power with SAIF ...
  LUT=934 FF=1071 | Pdyn=0.030 W Pstatic=0.090 W Ptotal=0.120 W | confidence=High | nets matched: 72%   (1819/2530)

================ SUMMARY (plain text) ================
V0_xoshiro_only: LUT=685 FF=847 Pdyn=0.027W Pstatic=0.090W Ptotal=0.117W pJ/bit(dyn)=4.64 pJ/bit(total)=20.11 confidence=High nets_matched=71%   (1373/1929) words=20000
V1_plus_weyl: LUT=853 FF=975 Pdyn=0.040W Pstatic=0.090W Ptotal=0.130W pJ/bit(dyn)=6.88 pJ/bit(total)=22.34 confidence=High nets_matched=75%   (1775/2357) words=20000
V2_plus_tent: LUT=794 FF=943 Pdyn=0.037W Pstatic=0.090W Ptotal=0.127W pJ/bit(dyn)=6.36 pJ/bit(total)=21.83 confidence=High nets_matched=67%   (1426/2136) words=20000
V3_full_original: LUT=934 FF=1071 Pdyn=0.030W Pstatic=0.090W Ptotal=0.120W pJ/bit(dyn)=5.16 pJ/bit(total)=20.63 confidence=High nets_matched=72%   (1819/2530) words=20000

================ LaTeX rows ================
V0\_xoshiro\_only & 685 & 847 & 0.027 & 4.64 & 20.11 \\
V1\_plus\_weyl & 853 & 975 & 0.040 & 6.88 & 22.34 \\
V2\_plus\_tent & 794 & 943 & 0.037 & 6.36 & 21.83 \\
V3\_full\_original & 934 & 1071 & 0.030 & 5.16 & 20.63 \\

Method (for the manuscript): post-implementation gate-level timing simulation (xsim, SDF back-annotated),
20000 output words at 181.82 MHz, TREADY duty 100 %, zero key = False, warm-up 5, SAIF -> Vivado report_power.
Same flow, same stimulus, same part for all variants. pJ/bit = power / (32 bit x 181.82 MHz).
SAIF run finished: 2026-11-02T22:39:39
